Low leakage one transistor static random access memory

ABSTRACT

The invention forms a 1T Static Random Access Memory (SRAM) with a low concentration cell node region and a higher concentration bit line region (e.g., second bit line region). The method of the invention forms a 1T Static Random Access Memory (SRAM) that uses a resist mask to block a high concentration implant into the cell node region, but allows the high concentration implant into the bit line region to form a second (high concentration) bit line. The invention&#39;s 1T SRAM, with the low concentration cell node, has reduced p-n junction leakage at the cell node and increase date retention time.

BACKGROUND OF INVENTION

1) Field of the Invention

This invention relates generally to fabrication semiconductor memorydevices and particularly to the structure of a one transistor (1T)Static Random Access Memory (SRAM) cell.

2) Description of the Prior Art

FIG. 1 shows a schematic of a one transistor (1T) Static Random AccessMemory (SRAM) cell. The 1T SRAM is designed for high speed and low costlogic products. However, the inventors have found that the 1 T SRAM cellhas performance degradation that can be reduced.

The importance of overcoming the various deficiencies noted above isevidenced by the extensive technological development directed to thesubject, as documented by the relevant patent and technical literature.The closest and apparently more relevant technical developments in thepatent literature can be gleaned by considering U.S. Pat. No. 5,686,336(Lee) shows a 4T SRAM layout. U.S. Pat. No. 6,078,087 (Huang et al.) andU.S. Pat. No. 5,953,606 (Huang et al.) shows TFT SRAM layouts.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a method forfabricating a 1T SRAM with low leakage.

It is an object of the present invention to provide a method forfabricating a 1T SRAM with low leakage using a P minus (P−) region onthe cell storage node.

It is an object of the present invention to provide a method forfabricating a 1T SRAM with a revised cell layout with a blocked P plus(P+) S/D ion implant (I/I) on the cell storage node n-p junction.

The invention forms 1T Static Random Access Memory (SRAM) with a lowconcentration cell node region and a higher concentration bit lineregion (e.g., second bit line region).

To accomplish the above objectives, the present invention provides astructure for a 1T SRAM which is characterized:

-   -   a word line structure and a capacitor plate structure on a        substrate; a cell node in the substrate between the word line        structure and the capacitor plate structure; a bit line region        in the substrate adjacent to the word line structure,    -   a capacitor plate structure is comprised of a capacitor        dielectric on the substrate and a conductive plate layer on the        capacitor dielectric; the capacitor plate structure overlying a        plate region of the substrate; the plate region and the        conductive plate layer acting as one plates of a capacitor;    -   the bit line region consists of a first bit line region and a        second bit line (lightly doped) region; the first bit line        region has the same impurity concentration as the cell node; the        second bit line region has an impurity concentration (e.g.,        atoms/cc) greater than the cell node by preferably at least an        order of 10.

The inventors have found an unexpected increase in the performance ofthe SRAM with the low concentration cell node region and the second(higher concentration) bit line. The inventors have found that the 1 TSRAM cell has performance degradation due to the high junction leakageon cell storage node. By blocking the P+ implant into the cell node, then-p junction (cell node junction) leakage was reduced and the cell dataretention time increased.

The present invention achieves these benefits in the context of knownprocess technology. However, a further understanding of the nature andadvantages of the present invention may be realized by reference to thelatter portions of the specification and attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The features and advantages of a semiconductor device according to thepresent invention and further details of a process of fabricating such asemiconductor device in accordance with the present invention will bemore clearly understood from the following description taken inconjunction with the accompanying drawings in which like referencenumerals designate similar or corresponding elements, regions andportions and in which:

FIG. 1 shows a schematic of a one transistor (1T) Static Random AccessMemory (SRAM) cell according to the prior art.

FIGS. 2 through 4 are cross sectional views for illustrating a methodfor manufacturing a preferred embodiment of the 1T Static Random AccessMemory (SRAM) according to the present invention.

FIG. 5 is a top down view of a preferred embodiment of the 1T StaticRandom Access Memory (SRAM) according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

I. Method for 1T Static Random Access Memory (SRAM)

The method of fabrication of a 1T SRAM is shown in cross sectional FIGS.2 to 4 and top down FIG. 5.

As shown in FIGS. 2 and 5, shallow trench isolations (STI) 14 are formedin the substrate 10 using conventional processes. FIG. 5 shows a topdown view. STI regions 14 are located around the devices for isolation.

The substrate can be any semiconductor substrate. Preferably thesubstrate is a silicon wafer that is doped with a p type impurity suchas boron (B) to a concentration of between 5E14 and 1E15 atoms/cc. Inthe FIGS, the substrate 10 can have a n-type well (not shown) that the1T SRAM is formed on. That is the substrate 10 can represent a waferwith a N-well (second conductivity type is n-type) with a concentrationbetween 1E17 and 1E18 atoms/cc near the invention's subsequently formed1T SRAM. Preferably the region in the substrate surrounding theinvention's subsequently formed 1T SRAM has a n-type doping (e.g.,second conductivity type is n-type) with a concentration between 1E17and 1E18 atoms/cc.

A. Word Line Structure 18 24 and a Capacitor Plate Structure 20 30

Next, a word line structure 18 24 and a capacitor plate structure 20 30are formed on a substrate 10.

A dielectric layer and a conductive layer are formed over the substrate.Next, the dielectric layer and the conductive layer are patterned toform the word line structure 18 24 and a capacitor plate structure 2030. The dielectric layer is preferably comprised of oxide having athickness of between about 40 and 60 Å. The conductive layer ispreferably comprised of polysilicon and preferably has a thickness ofbetween about 1500 and 2500 Å.

The capacitor plate structure 20 30 is comprised of a capacitordielectric 20 on the substrate 10 and a conductive plate layer 30 on thecapacitor dielectric 20. The capacitor plate structure 20 30 overlying aplate region of the substrate. The plate region and the conductive platelayer 30 act as plates of a capacitor.

B. LDD I/I—Cell Node Region 40 and First Bit Line Region 34

As shown in FIG. 2, in a key step, we implant ions of a firstconductivity type (e.g., p type) into the substrate forming a cell noderegion 40 in the substrate 10 between the word line structure 18 24 andthe capacitor plate structure 20 30; and forming a first bit line region34 in the substrate adjacent to the word line structure 18 24. The cellnode region 40 and the first bit line region 34 preferably do notintersect.

In a preferred embodiment, both the cell node region 40 and the firstbit line region 34 (low conc) have a p-type doping and have an impurityconcentration between 1E17 and 1E19 atoms/CC and more preferably between1E18 and 1E19 atoms/CC. This low impurity concentration is at the pminus (p−) level.

In another embodiment, the cell node region 40 and the first bit lineregion 34 can be formed with two separate ion implant steps (e.g., maskthe non-implanted areas). This allows the cell node region 40 and thefirst bit line region 34 to have different concentrations. For example,the first bit line region 34 can have a concentration between 1E18 and1E19 atoms/cc and the cell node region 40 can have a concentrationbetween 1E17 and 1E18 atoms/cc.

C. Spacer

Referring to FIG. 3, we form spacers 46 and 50 on the sidewalls of theword line structure 18 24 and the capacitor plate structure 20 30. Thespacer are preferably formed of oxide or nitride and are formed byconventional means.

D. Resist 56 to Block P+ I/I

In a critical step in the invention, as shown in FIG. 3, we form a mask(e.g., resist) pattern 56 over the cell node 40. Any implant blockingmask can be used. This resist pattern servers to block a subsequent highconcentration (e.g., P+) implant into the bit line region.

E. P+ Implant into Bit Line

Next, we implant ions of a first conductivity type into the substrate toform a high concentration bitline 60. The high concentration bitline 60preferably has p-type doping (e.g., boron) and preferably has aconcentration between 1E20 and 1E21 Atom/cc. This is at the P plus (p+)doping level. It is critical that these ions are not implanted into thecell node 40.

The second bit line region 60 preferably has an impurity concentrationgreater than the cell node region 40 by at least a factor of 10.

The inventors have found an unexpected increase in the performance ofthe SRAM with the low concentration cell node region 40 and the second(higher concentration) bit line 60. By blocking the P plus (P+) implantinto the cell node, the n-p junction (cell node junction) leakage wasunexpectedly and dramatically reduced and the cell data retention timeincreased.

F. FIG. 4—Form a Bitline Contact 68

Next, the resist 56 is removed.

As shown in FIG. 4, we form a dielectric layer (e.g., IDLO) 52 over thesubstrate.

A shown in FIGS. 4 and 5, we form a bitline contact 68 to the highconcentration bitline 60. Other contacts (not shown) are formed to theother elements (e.g., cell node, word line etc.).

FIG. 5 is a top down view of a preferred embodiment of the 1T StaticRandom Access Memory (SRAM) according to the present invention.

II. Description of the 1T SRAM Structure

The present invention provides a structure for a 1T SRAM which ischaracterized as follows. FIG. 4 shows a cross sectional view of the 1TSRAM and FIG. 5 shows a top down view.

As shown in FIGS. 4 and 5, a word line structure 18 24 and a capacitorplate structure 20 30 are on a substrate 10. A cell node region 40 is inthe substrate 10 between the word line structure and the capacitor platestructure 20 30. A bit line region 34 60 is in the substrate adjacent tothe word line structure 18 24. The cell node region 40 and the bit lineregion 34 do not intersect.

The capacitor plate structure 20 30 is preferably comprised of acapacitor dielectric 20 on the substrate 10 and a conductive plate layer30 on the capacitor dielectric 20. The capacitor plate structure 20 30overlies a plate region of the substrate 10. The plate region and theconductive plate layer 30 act as one plate of a capacitor.

The bit line region 34 60 consists of a first bit line region 34 and asecond bit line (lightly doped) region 60. The first bit line region 34has about the same impurity concentration as the cell node 40.

A critical element of the invention is that the second bit line region60 has an impurity concentration greater than the cell node 40 by atleast a factor of 10 atoms/cc. In a preferred embodiment, the first bitline region 34 (low conc) has a p-type doping and has a impurityconcentration between 1E18 and 1E19 atom/cm³, the second bit line region(high conc) 60 has a p-type doping and has a impurity concentrationbetween 1E20 and 1E21 atom/cc and the cell node region 40 has a p-typedoping and has an impurity concentration between 1E17 and 1E18 atom/cc.

The second bit line 60 has an impurity concentration preferably greaterthan the cell node region 40 by at least a factor of 10.

FIG. 5 shows a top down view. STI regions 14 are located around thedevices for isolation.

In the above description numerous specific details are set forth such asflow rates, pressure settings, thicknesses, etc., in order to provide amore thorough understanding of the present invention. It will beobvious, however, to one skilled in the art that the present inventionmay be practiced without these details. In other instances, well knownprocess have not been described in detail in order to not unnecessarilyobscure the present invention.

Although this invention has been described relative to specificinsulating materials, conductive materials and apparatuses fordepositing and etching these materials, it is not limited to thespecific materials or apparatuses but only to their specificcharacteristics, such as conformal and nonconformal, and capabilities,such as depositing and etching, and other materials and apparatus can besubstituted as is well understood by those skilled in themicroelectronics arts after appreciating the present invention

Unless explicitly stated otherwise, each numerical value and rangeshould be interpreted as being approximate as if the word “about” or“approximately” preceded the value of the value or range.

While the invention has been particularly shown and described withreference to the preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade without departing from the spirit and scope of the invention. It isintended to cover various modifications and similar arrangements andprocedures, and the scope of the appended claims therefore should beaccorded the broadest interpretation so as to encompass all suchmodifications and similar arrangements and procedures.

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 10. The 1T SRAM ofclaim 15 wherein said substrate is doped with an n-type impurity; saidsubstrate having an impurity concentration between 1E17 and 1E18atoms/cc.
 11. The 1T SRAM of claim 15 wherein said substrate is p dopedand has a n-well under said word line structure and said capacitor platestructure; said n-well is doped with an n-type impurity; said n-well hasan impurity concentration between 1E17 and 1E18 atoms/cc.
 12. (Canceled)13. (Canceled)
 14. (Canceled)
 15. A 1T SRAM comprising: a word linestructure on a substrate; a capacitor plate structure on said substrate;a cell node region in said substrate between said word line structureand said capacitor plate structure, said cell node region having animpurity concentration; and a bit line region in said substrate adjacentto said word line structure; wherein said bit line region includes afirst region having an impurity concentration greater than the impurityconcentration of said cell node region.
 16. The 1T SRAM of claim 15wherein said cell node region and said bit line region do not intersect.17. The 1T SRAM of claim 15 wherein said capacitor plate structurecomprises: a conductive plate region of said substrate; a capacitordielectric disposed on said substrate; and a conductive plate layerdisposed on said capacitor dielectric.
 18. The 1T SRAM of claim 15wherein said bit line region further comprises a second region having animpurity concentration which is substantially the same as the impurityconcentration of said cell node region.
 19. The 1T SRAM of claim 15,wherein said impurity concentration of said first region of said bitline region is greater than the impurity concentration of said cell noderegion by at least a factor of
 10. 20. The 1T SRAM of claim 15 whereinsaid first region of said bit line region has a p-type doping and aimpurity concentration between 1E20 and 1E21 atoms/cc.
 21. The 1T SRAMof claim 18 wherein said second region of said bit line region and saidcell node region each have a p-type doping and an impurity concentrationbetween 1E17 and 1E19 atoms/cc.